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Package loong64

import "cmd/internal/obj/loong64"
Overview
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Overview ▾

Package loong64 implements an LoongArch64 assembler. Go assembly syntax is different from GNU LoongArch64 syntax, but we can still follow the general rules to map between them.

Instructions mnemonics mapping rules

1. Bit widths represented by various instruction suffixes and prefixes V (vlong) = 64 bit WU (word) = 32 bit unsigned W (word) = 32 bit H (half word) = 16 bit HU = 16 bit unsigned B (byte) = 8 bit BU = 8 bit unsigned F (float) = 32 bit float D (double) = 64 bit float

V (LSX) = 128 bit XV (LASX) = 256 bit

Examples: 

MOVB  (R2), R3  // Load 8 bit memory data into R3 register
MOVH  (R2), R3  // Load 16 bit memory data into R3 register
MOVW  (R2), R3  // Load 32 bit memory data into R3 register
MOVV  (R2), R3  // Load 64 bit memory data into R3 register
VMOVQ  (R2), V1 // Load 128 bit memory data into V1 register
XVMOVQ (R2), X1 // Load 256 bit memory data into X1 register

2. Align directive Go asm supports the PCALIGN directive, which indicates that the next instruction should be aligned to a specified boundary by padding with NOOP instruction. The alignment value supported on loong64 must be a power of 2 and in the range of [8, 2048].

Examples: 

PCALIGN	$16
MOVV	$2, R4	// This instruction is aligned with 16 bytes.
PCALIGN	$1024
MOVV	$3, R5	// This instruction is aligned with 1024 bytes.

On loong64, auto-align loop heads to 16-byte boundaries

Examples: 

TEXT ·Add(SB),NOSPLIT|NOFRAME,$0

start: 

MOVV	$1, R4	// This instruction is aligned with 16 bytes.
MOVV	$-1, R5
BNE	R5, start
RET

Register mapping rules

1. All generial-prupose register names are written as Rn.

2. All floating-point register names are written as Fn.

3. All LSX register names are written as Vn.

4. All LASX register names are written as Xn.

Argument mapping rules

1. The operands appear in left-to-right assignment order.

Go reverses the arguments of most instructions.

Examples: 

ADDV	R11, R12, R13 <=> add.d R13, R12, R11
LLV	(R4), R7      <=> ll.d R7, R4
OR	R5, R6        <=> or R6, R6, R5

Special Cases. (1) Argument order is the same as in the GNU Loong64 syntax: jump instructions,

Examples: 

BEQ	R0, R4, lable1  <=>  beq R0, R4, lable1
JMP	lable1          <=>  b lable1

(2) BSTRINSW, BSTRINSV, BSTRPICKW, BSTRPICKV $<msb>, <Rj>, $<lsb>, <Rd>

Examples: 

BSTRPICKW $15, R4, $6, R5  <=>  bstrpick.w r5, r4, 15, 6

2. Expressions for special arguments.

Memory references: a base register and an offset register is written as (Rbase)(Roff).

Examples: 

MOVB (R4)(R5), R6  <=>  ldx.b R6, R4, R5
MOVV (R4)(R5), R6  <=>  ldx.d R6, R4, R5
MOVD (R4)(R5), F6  <=>  fldx.d F6, R4, R5
MOVB R6, (R4)(R5)  <=>  stx.b R6, R5, R5
MOVV R6, (R4)(R5)  <=>  stx.d R6, R5, R5
MOVV F6, (R4)(R5)  <=>  fstx.d F6, R5, R5

3. Alphabetical list of SIMD instructions

Note: In the following sections 3.1 to 3.6, "ui4" (4-bit unsigned int immediate), "ui3", "ui2", and "ui1" represent the related "index".

3.1 Move general-purpose register to a vector element: 

Instruction format:
        VMOVQ  Rj, <Vd>.<T>[index]

Mapping between Go and platform assembly:
       Go assembly       |      platform assembly     |          semantics
-------------------------------------------------------------------------------------
 VMOVQ  Rj, Vd.B[index]  |  vinsgr2vr.b  Vd, Rj, ui4  |  VR[vd].b[ui4] = GR[rj][7:0]
 VMOVQ  Rj, Vd.H[index]  |  vinsgr2vr.h  Vd, Rj, ui3  |  VR[vd].h[ui3] = GR[rj][15:0]
 VMOVQ  Rj, Vd.W[index]  |  vinsgr2vr.w  Vd, Rj, ui2  |  VR[vd].w[ui2] = GR[rj][31:0]
 VMOVQ  Rj, Vd.V[index]  |  vinsgr2vr.d  Vd, Rj, ui1  |  VR[vd].d[ui1] = GR[rj][63:0]
XVMOVQ  Rj, Xd.W[index]  | xvinsgr2vr.w  Xd, Rj, ui3  |  XR[xd].w[ui3] = GR[rj][31:0]
XVMOVQ  Rj, Xd.V[index]  | xvinsgr2vr.d  Xd, Rj, ui2  |  XR[xd].d[ui2] = GR[rj][63:0]

3.2 Move vector element to general-purpose register 

Instruction format:
        VMOVQ     <Vj>.<T>[index], Rd

Mapping between Go and platform assembly:
        Go assembly       |       platform assembly      |            semantics
---------------------------------------------------------------------------------------------
 VMOVQ  Vj.B[index],  Rd  |   vpickve2gr.b   rd, vj, ui4 | GR[rd] = SignExtend(VR[vj].b[ui4])
 VMOVQ  Vj.H[index],  Rd  |   vpickve2gr.h   rd, vj, ui3 | GR[rd] = SignExtend(VR[vj].h[ui3])
 VMOVQ  Vj.W[index],  Rd  |   vpickve2gr.w   rd, vj, ui2 | GR[rd] = SignExtend(VR[vj].w[ui2])
 VMOVQ  Vj.V[index],  Rd  |   vpickve2gr.d   rd, vj, ui1 | GR[rd] = SignExtend(VR[vj].d[ui1])
 VMOVQ  Vj.BU[index], Rd  |   vpickve2gr.bu  rd, vj, ui4 | GR[rd] = ZeroExtend(VR[vj].bu[ui4])
 VMOVQ  Vj.HU[index], Rd  |   vpickve2gr.hu  rd, vj, ui3 | GR[rd] = ZeroExtend(VR[vj].hu[ui3])
 VMOVQ  Vj.WU[index], Rd  |   vpickve2gr.wu  rd, vj, ui2 | GR[rd] = ZeroExtend(VR[vj].wu[ui2])
 VMOVQ  Vj.VU[index], Rd  |   vpickve2gr.du  rd, vj, ui1 | GR[rd] = ZeroExtend(VR[vj].du[ui1])
XVMOVQ  Xj.W[index],  Rd  |  xvpickve2gr.w   rd, xj, ui3 | GR[rd] = SignExtend(VR[xj].w[ui3])
XVMOVQ  Xj.V[index],  Rd  |  xvpickve2gr.d   rd, xj, ui2 | GR[rd] = SignExtend(VR[xj].d[ui2])
XVMOVQ  Xj.WU[index], Rd  |  xvpickve2gr.wu  rd, xj, ui3 | GR[rd] = ZeroExtend(VR[xj].wu[ui3])
XVMOVQ  Xj.VU[index], Rd  |  xvpickve2gr.du  rd, xj, ui2 | GR[rd] = ZeroExtend(VR[xj].du[ui2])

3.3 Duplicate general-purpose register to vector. 

Instruction format:
        VMOVQ    Rj, <Vd>.<T>

Mapping between Go and platform assembly:
   Go assembly      |    platform assembly    |                    semantics
------------------------------------------------------------------------------------------------
 VMOVQ  Rj, Vd.B16  |   vreplgr2vr.b  Vd, Rj  |  for i in range(16): VR[vd].b[i] = GR[rj][7:0]
 VMOVQ  Rj, Vd.H8   |   vreplgr2vr.h  Vd, Rj  |  for i in range(8) : VR[vd].h[i] = GR[rj][16:0]
 VMOVQ  Rj, Vd.W4   |   vreplgr2vr.w  Vd, Rj  |  for i in range(4) : VR[vd].w[i] = GR[rj][31:0]
 VMOVQ  Rj, Vd.V2   |   vreplgr2vr.d  Vd, Rj  |  for i in range(2) : VR[vd].d[i] = GR[rj][63:0]
XVMOVQ  Rj, Xd.B32  |  xvreplgr2vr.b  Xd, Rj  |  for i in range(32): XR[xd].b[i] = GR[rj][7:0]
XVMOVQ  Rj, Xd.H16  |  xvreplgr2vr.h  Xd, Rj  |  for i in range(16): XR[xd].h[i] = GR[rj][16:0]
XVMOVQ  Rj, Xd.W8   |  xvreplgr2vr.w  Xd, Rj  |  for i in range(8) : XR[xd].w[i] = GR[rj][31:0]
XVMOVQ  Rj, Xd.V4   |  xvreplgr2vr.d  Xd, Rj  |  for i in range(4) : XR[xd].d[i] = GR[rj][63:0]

3.4 Replace vector elements 

Instruction format:
        XVMOVQ    Xj, <Xd>.<T>

Mapping between Go and platform assembly:
   Go assembly      |   platform assembly   |                semantics
------------------------------------------------------------------------------------------------
XVMOVQ  Xj, Xd.B32  |  xvreplve0.b  Xd, Xj  | for i in range(32): XR[xd].b[i] = XR[xj].b[0]
XVMOVQ  Xj, Xd.H16  |  xvreplve0.h  Xd, Xj  | for i in range(16): XR[xd].h[i] = XR[xj].h[0]
XVMOVQ  Xj, Xd.W8   |  xvreplve0.w  Xd, Xj  | for i in range(8) : XR[xd].w[i] = XR[xj].w[0]
XVMOVQ  Xj, Xd.V4   |  xvreplve0.d  Xd, Xj  | for i in range(4) : XR[xd].d[i] = XR[xj].d[0]
XVMOVQ  Xj, Xd.Q2   |  xvreplve0.q  Xd, Xj  | for i in range(2) : XR[xd].q[i] = XR[xj].q[0]

3.5 Move vector element to scalar 

Instruction format:
        XVMOVQ  Xj, <Xd>.<T>[index]
        XVMOVQ  Xj.<T>[index], Xd

Mapping between Go and platform assembly:
       Go assembly        |     platform assembly     |               semantics
------------------------------------------------------------------------------------------------
 XVMOVQ  Xj, Xd.W[index]  |  xvinsve0.w   xd, xj, ui3 | XR[xd].w[ui3] = XR[xj].w[0]
 XVMOVQ  Xj, Xd.V[index]  |  xvinsve0.d   xd, xj, ui2 | XR[xd].d[ui2] = XR[xj].d[0]
 XVMOVQ  Xj.W[index], Xd  |  xvpickve.w   xd, xj, ui3 | XR[xd].w[0] = XR[xj].w[ui3], XR[xd][255:32] = 0
 XVMOVQ  Xj.V[index], Xd  |  xvpickve.d   xd, xj, ui2 | XR[xd].d[0] = XR[xj].d[ui2], XR[xd][255:64] = 0

3.6 Move vector element to vector register. 

Instruction format:
VMOVQ     <Vn>.<T>[index], Vn.<T>

Mapping between Go and platform assembly:
         Go assembly      |    platform assembly   |               semantics
VMOVQ Vj.B[index], Vd.B16 | vreplvei.b vd, vj, ui4 | for i in range(16): VR[vd].b[i] = VR[vj].b[ui4]
VMOVQ Vj.H[index], Vd.H8  | vreplvei.h vd, vj, ui3 | for i in range(8) : VR[vd].h[i] = VR[vj].h[ui3]
VMOVQ Vj.W[index], Vd.W4  | vreplvei.w vd, vj, ui2 | for i in range(4) : VR[vd].w[i] = VR[vj].w[ui2]
VMOVQ Vj.V[index], Vd.V2  | vreplvei.d vd, vj, ui1 | for i in range(2) : VR[vd].d[i] = VR[vj].d[ui1]

Special instruction encoding definition and description on LoongArch

  1. DBAR hint encoding for LA664(Loongson 3A6000) and later micro-architectures, paraphrased from the Linux kernel implementation: https://git.kernel.org/torvalds/c/e031a5f3f1ed

    - Bit4: ordering or completion (0: completion, 1: ordering) - Bit3: barrier for previous read (0: true, 1: false) - Bit2: barrier for previous write (0: true, 1: false) - Bit1: barrier for succeeding read (0: true, 1: false) - Bit0: barrier for succeeding write (0: true, 1: false) - Hint 0x700: barrier for "read after read" from the same address

    Traditionally, on microstructures that do not support dbar grading such as LA464 (Loongson 3A5000, 3C5000) all variants are treated as “dbar 0” (full barrier).

2. Notes on using atomic operation instructions

  • AM*_DB.W[U]/V[U] instructions such as AMSWAPDBW not only complete the corresponding atomic operation sequence, but also implement the complete full data barrier function.

  • When using the AM*_.W[U]/D[U] instruction, registers rd and rj cannot be the same, otherwise an exception is triggered, and rd and rk cannot be the same, otherwise the execution result is uncertain.

Constants

const (
    NSNAME = 8
    NSYM   = 50
    NREG   = 32 // number of general registers
    NFREG  = 32 // number of floating point registers
    NVREG  = 32 // number of LSX registers
    NXREG  = 32 // number of LASX registers
)
const (
    REG_R0 = obj.RBaseLOONG64 + iota // must be a multiple of 32
    REG_R1
    REG_R2
    REG_R3
    REG_R4
    REG_R5
    REG_R6
    REG_R7
    REG_R8
    REG_R9
    REG_R10
    REG_R11
    REG_R12
    REG_R13
    REG_R14
    REG_R15
    REG_R16
    REG_R17
    REG_R18
    REG_R19
    REG_R20
    REG_R21
    REG_R22
    REG_R23
    REG_R24
    REG_R25
    REG_R26
    REG_R27
    REG_R28
    REG_R29
    REG_R30
    REG_R31

    REG_F0 // must be a multiple of 32
    REG_F1
    REG_F2
    REG_F3
    REG_F4
    REG_F5
    REG_F6
    REG_F7
    REG_F8
    REG_F9
    REG_F10
    REG_F11
    REG_F12
    REG_F13
    REG_F14
    REG_F15
    REG_F16
    REG_F17
    REG_F18
    REG_F19
    REG_F20
    REG_F21
    REG_F22
    REG_F23
    REG_F24
    REG_F25
    REG_F26
    REG_F27
    REG_F28
    REG_F29
    REG_F30
    REG_F31

    REG_FCSR0 // must be a multiple of 32
    REG_FCSR1
    REG_FCSR2
    REG_FCSR3 // only four registers are needed
    REG_FCSR4
    REG_FCSR5
    REG_FCSR6
    REG_FCSR7
    REG_FCSR8
    REG_FCSR9
    REG_FCSR10
    REG_FCSR11
    REG_FCSR12
    REG_FCSR13
    REG_FCSR14
    REG_FCSR15
    REG_FCSR16
    REG_FCSR17
    REG_FCSR18
    REG_FCSR19
    REG_FCSR20
    REG_FCSR21
    REG_FCSR22
    REG_FCSR23
    REG_FCSR24
    REG_FCSR25
    REG_FCSR26
    REG_FCSR27
    REG_FCSR28
    REG_FCSR29
    REG_FCSR30
    REG_FCSR31

    REG_FCC0 // must be a multiple of 32
    REG_FCC1
    REG_FCC2
    REG_FCC3
    REG_FCC4
    REG_FCC5
    REG_FCC6
    REG_FCC7 // only eight registers are needed
    REG_FCC8
    REG_FCC9
    REG_FCC10
    REG_FCC11
    REG_FCC12
    REG_FCC13
    REG_FCC14
    REG_FCC15
    REG_FCC16
    REG_FCC17
    REG_FCC18
    REG_FCC19
    REG_FCC20
    REG_FCC21
    REG_FCC22
    REG_FCC23
    REG_FCC24
    REG_FCC25
    REG_FCC26
    REG_FCC27
    REG_FCC28
    REG_FCC29
    REG_FCC30
    REG_FCC31

    // LSX: 128-bit vector register
    REG_V0
    REG_V1
    REG_V2
    REG_V3
    REG_V4
    REG_V5
    REG_V6
    REG_V7
    REG_V8
    REG_V9
    REG_V10
    REG_V11
    REG_V12
    REG_V13
    REG_V14
    REG_V15
    REG_V16
    REG_V17
    REG_V18
    REG_V19
    REG_V20
    REG_V21
    REG_V22
    REG_V23
    REG_V24
    REG_V25
    REG_V26
    REG_V27
    REG_V28
    REG_V29
    REG_V30
    REG_V31

    // LASX: 256-bit vector register
    REG_X0
    REG_X1
    REG_X2
    REG_X3
    REG_X4
    REG_X5
    REG_X6
    REG_X7
    REG_X8
    REG_X9
    REG_X10
    REG_X11
    REG_X12
    REG_X13
    REG_X14
    REG_X15
    REG_X16
    REG_X17
    REG_X18
    REG_X19
    REG_X20
    REG_X21
    REG_X22
    REG_X23
    REG_X24
    REG_X25
    REG_X26
    REG_X27
    REG_X28
    REG_X29
    REG_X30
    REG_X31

    REG_SPECIAL = REG_FCSR0

    REGZERO = REG_R0 // set to zero
    REGLINK = REG_R1
    REGSP   = REG_R3
    REGRET  = REG_R20 // not use
    REGARG  = -1      // -1 disables passing the first argument in register
    REGRT1  = REG_R20 // reserved for runtime, duffzero and duffcopy
    REGRT2  = REG_R21 // reserved for runtime, duffcopy
    REGCTXT = REG_R29 // context for closures
    REGG    = REG_R22 // G in loong64
    REGTMP  = REG_R30 // used by the assembler
    FREGRET = REG_F0  // not use
)
const (
    // mark flags
    LABEL  = 1 << 0
    LEAF   = 1 << 1
    SYNC   = 1 << 2
    BRANCH = 1 << 3
)

Arrangement for Loong64 SIMD instructions 

const (
    // arrangement types
    ARNG_32B int16 = iota
    ARNG_16H
    ARNG_8W
    ARNG_4V
    ARNG_2Q
    ARNG_16B
    ARNG_8H
    ARNG_4W
    ARNG_2V
    ARNG_B
    ARNG_H
    ARNG_W
    ARNG_V
    ARNG_BU
    ARNG_HU
    ARNG_WU
    ARNG_VU
)

LoongArch64 SIMD extension type 

const (
    LSX int16 = iota
    LASX
)

bits 0-4 indicates register: Vn or Xn bits 5-9 indicates arrangement: <T> bits 10 indicates SMID type: 0: LSX, 1: LASX 

const (
    REG_ARNG = obj.RBaseLOONG64 + (1 << 10) + (iota << 11) // Vn.<T>
    REG_ELEM                                               // Vn.<T>[index]
    REG_ELEM_END
)
const (
    EXT_REG_SHIFT = 0
    EXT_REG_MASK  = 0x1f

    EXT_TYPE_SHIFT = 5
    EXT_TYPE_MASK  = 0x1f

    EXT_SIMDTYPE_SHIFT = 10
    EXT_SIMDTYPE_MASK  = 0x1
)
const (
    C_NONE = iota
    C_REG
    C_FREG
    C_FCSRREG
    C_FCCREG
    C_VREG
    C_XREG
    C_ARNG // Vn.<T>
    C_ELEM // Vn.<T>[index]
    C_ZCON
    C_SCON // 12 bit signed
    C_UCON // 32 bit signed, low 12 bits 0
    C_ADD0CON
    C_AND0CON
    C_ADDCON  // -0x800 <= v < 0
    C_ANDCON  // 0 < v <= 0xFFF
    C_LCON    // other 32
    C_DCON    // other 64 (could subdivide further)
    C_SACON   // $n(REG) where n <= int12
    C_LACON   // $n(REG) where int12 < n <= int32
    C_DACON   // $n(REG) where int32 < n
    C_EXTADDR // external symbol address
    C_BRAN
    C_SAUTO
    C_LAUTO
    C_ZOREG
    C_SOREG
    C_LOREG
    C_ROFF // register offset
    C_ADDR
    C_TLS_LE
    C_TLS_IE
    C_GOTADDR
    C_TEXTSIZE

    C_GOK
    C_NCLASS // must be the last
)
const (
    AABSD = obj.ABaseLoong64 + obj.A_ARCHSPECIFIC + iota
    AABSF
    AADD
    AADDD
    AADDF
    AADDU

    AADDW
    AAND
    ABEQ
    ABGEZ
    ABLEZ
    ABGTZ
    ABLTZ
    ABFPF
    ABFPT

    ABNE
    ABREAK

    ACMPEQD
    ACMPEQF

    ACMPGED // ACMPGED -> fcmp.sle.d
    ACMPGEF // ACMPGEF -> fcmp.sle.s
    ACMPGTD // ACMPGTD -> fcmp.slt.d
    ACMPGTF // ACMPGTF -> fcmp.slt.s

    ALU12IW
    ALU32ID
    ALU52ID
    APCALAU12I
    APCADDU12I
    AJIRL
    ABGE
    ABLT
    ABLTU
    ABGEU

    ADIV
    ADIVD
    ADIVF
    ADIVU
    ADIVW

    ALL
    ALLV

    ALUI

    AMOVB
    AMOVBU

    AMOVD
    AMOVDF
    AMOVDW
    AMOVF
    AMOVFD
    AMOVFW

    AMOVH
    AMOVHU
    AMOVW

    AMOVWD
    AMOVWF

    AMUL
    AMULD
    AMULF
    AMULU
    AMULH
    AMULHU
    AMULW
    ANEGD
    ANEGF

    ANEGW
    ANEGV

    ANOOP // hardware nop
    ANOR
    AOR
    AREM
    AREMU

    ARFE

    ASC
    ASCV

    ASGT
    ASGTU

    ASLL
    ASQRTD
    ASQRTF
    ASRA
    ASRL
    AROTR
    ASUB
    ASUBD
    ASUBF

    ASUBU
    ASUBW
    ADBAR
    ASYSCALL

    ATEQ
    ATNE

    AWORD

    AXOR

    AMASKEQZ
    AMASKNEZ

    // 64-bit
    AMOVV

    ASLLV
    ASRAV
    ASRLV
    AROTRV
    ADIVV
    ADIVVU

    AREMV
    AREMVU

    AMULV
    AMULVU
    AMULHV
    AMULHVU
    AADDV
    AADDVU
    ASUBV
    ASUBVU

    // 64-bit FP
    ATRUNCFV
    ATRUNCDV
    ATRUNCFW
    ATRUNCDW

    AMOVWU
    AMOVFV
    AMOVDV
    AMOVVF
    AMOVVD

    // 2.2.1.8
    AORN
    AANDN

    // 2.2.7. Atomic Memory Access Instructions
    AAMSWAPB
    AAMSWAPH
    AAMSWAPW
    AAMSWAPV
    AAMCASB
    AAMCASH
    AAMCASW
    AAMCASV
    AAMADDW
    AAMADDV
    AAMANDW
    AAMANDV
    AAMORW
    AAMORV
    AAMXORW
    AAMXORV
    AAMMAXW
    AAMMAXV
    AAMMINW
    AAMMINV
    AAMMAXWU
    AAMMAXVU
    AAMMINWU
    AAMMINVU
    AAMSWAPDBB
    AAMSWAPDBH
    AAMSWAPDBW
    AAMSWAPDBV
    AAMCASDBB
    AAMCASDBH
    AAMCASDBW
    AAMCASDBV
    AAMADDDBW
    AAMADDDBV
    AAMANDDBW
    AAMANDDBV
    AAMORDBW
    AAMORDBV
    AAMXORDBW
    AAMXORDBV
    AAMMAXDBW
    AAMMAXDBV
    AAMMINDBW
    AAMMINDBV
    AAMMAXDBWU
    AAMMAXDBVU
    AAMMINDBWU
    AAMMINDBVU

    // 2.2.3.1
    AEXTWB
    AEXTWH

    // 2.2.3.2
    ACLOW
    ACLOV
    ACLZW
    ACLZV
    ACTOW
    ACTOV
    ACTZW
    ACTZV

    // 2.2.3.4
    AREVBV
    AREVB2W
    AREVB4H
    AREVB2H

    // 2.2.3.5
    AREVH2W
    AREVHV

    // 2.2.3.6
    ABITREV4B
    ABITREV8B

    // 2.2.3.7
    ABITREVW
    ABITREVV

    // 2.2.3.8
    ABSTRINSW
    ABSTRINSV

    // 2.2.3.9
    ABSTRPICKW
    ABSTRPICKV

    // 2.2.9. CRC Check Instructions
    ACRCWBW
    ACRCWHW
    ACRCWWW
    ACRCWVW
    ACRCCWBW
    ACRCCWHW
    ACRCCWWW
    ACRCCWVW

    // 2.2.10. Other Miscellaneous Instructions
    ARDTIMELW
    ARDTIMEHW
    ARDTIMED
    ACPUCFG

    // 3.2.1.2
    AFMADDF
    AFMADDD
    AFMSUBF
    AFMSUBD
    AFNMADDF
    AFNMADDD
    AFNMSUBF
    AFNMSUBD

    // 3.2.1.3
    AFMINF
    AFMIND
    AFMAXF
    AFMAXD

    // 3.2.1.7
    AFCOPYSGF
    AFCOPYSGD
    AFSCALEBF
    AFSCALEBD
    AFLOGBF
    AFLOGBD

    // 3.2.1.8
    AFCLASSF
    AFCLASSD

    // 3.2.3.2
    AFFINTFW
    AFFINTFV
    AFFINTDW
    AFFINTDV
    AFTINTWF
    AFTINTWD
    AFTINTVF
    AFTINTVD

    // 3.2.3.3
    AFTINTRPWF
    AFTINTRPWD
    AFTINTRPVF
    AFTINTRPVD
    AFTINTRMWF
    AFTINTRMWD
    AFTINTRMVF
    AFTINTRMVD
    AFTINTRZWF
    AFTINTRZWD
    AFTINTRZVF
    AFTINTRZVD
    AFTINTRNEWF
    AFTINTRNEWD
    AFTINTRNEVF
    AFTINTRNEVD

    // LSX and LASX memory access instructions
    AVMOVQ
    AXVMOVQ

    // LSX and LASX Bit-manipulation Instructions
    AVPCNTB
    AVPCNTH
    AVPCNTW
    AVPCNTV
    AXVPCNTB
    AXVPCNTH
    AXVPCNTW
    AXVPCNTV

    // LSX and LASX integer comparison instruction
    AVSEQB
    AXVSEQB
    AVSEQH
    AXVSEQH
    AVSEQW
    AXVSEQW
    AVSEQV
    AXVSEQV

    ALAST

    // aliases
    AJMP = obj.AJMP
    AJAL = obj.ACALL
    ARET = obj.ARET
)
const (
    BIG = 2046
)
const (
    FuncAlign = 4
)
const (
    NOTUSETMP = 1 << iota // p expands to multiple instructions, but does NOT use REGTMP

)
const (
    REG_LAST = REG_ELEM_END // the last defined register
)

Variables

var Anames = []string{
    obj.A_ARCHSPECIFIC: "ABSD",
    "ABSF",
    "ADD",
    "ADDD",
    "ADDF",
    "ADDU",
    "ADDW",
    "AND",
    "BEQ",
    "BGEZ",
    "BLEZ",
    "BGTZ",
    "BLTZ",
    "BFPF",
    "BFPT",
    "BNE",
    "BREAK",
    "CMPEQD",
    "CMPEQF",
    "CMPGED",
    "CMPGEF",
    "CMPGTD",
    "CMPGTF",
    "LU12IW",
    "LU32ID",
    "LU52ID",
    "PCALAU12I",
    "PCADDU12I",
    "JIRL",
    "BGE",
    "BLT",
    "BLTU",
    "BGEU",
    "DIV",
    "DIVD",
    "DIVF",
    "DIVU",
    "DIVW",
    "LL",
    "LLV",
    "LUI",
    "MOVB",
    "MOVBU",
    "MOVD",
    "MOVDF",
    "MOVDW",
    "MOVF",
    "MOVFD",
    "MOVFW",
    "MOVH",
    "MOVHU",
    "MOVW",
    "MOVWD",
    "MOVWF",
    "MUL",
    "MULD",
    "MULF",
    "MULU",
    "MULH",
    "MULHU",
    "MULW",
    "NEGD",
    "NEGF",
    "NEGW",
    "NEGV",
    "NOOP",
    "NOR",
    "OR",
    "REM",
    "REMU",
    "RFE",
    "SC",
    "SCV",
    "SGT",
    "SGTU",
    "SLL",
    "SQRTD",
    "SQRTF",
    "SRA",
    "SRL",
    "ROTR",
    "SUB",
    "SUBD",
    "SUBF",
    "SUBU",
    "SUBW",
    "DBAR",
    "SYSCALL",
    "TEQ",
    "TNE",
    "WORD",
    "XOR",
    "MASKEQZ",
    "MASKNEZ",
    "MOVV",
    "SLLV",
    "SRAV",
    "SRLV",
    "ROTRV",
    "DIVV",
    "DIVVU",
    "REMV",
    "REMVU",
    "MULV",
    "MULVU",
    "MULHV",
    "MULHVU",
    "ADDV",
    "ADDVU",
    "SUBV",
    "SUBVU",
    "TRUNCFV",
    "TRUNCDV",
    "TRUNCFW",
    "TRUNCDW",
    "MOVWU",
    "MOVFV",
    "MOVDV",
    "MOVVF",
    "MOVVD",
    "ORN",
    "ANDN",
    "AMSWAPB",
    "AMSWAPH",
    "AMSWAPW",
    "AMSWAPV",
    "AMCASB",
    "AMCASH",
    "AMCASW",
    "AMCASV",
    "AMADDW",
    "AMADDV",
    "AMANDW",
    "AMANDV",
    "AMORW",
    "AMORV",
    "AMXORW",
    "AMXORV",
    "AMMAXW",
    "AMMAXV",
    "AMMINW",
    "AMMINV",
    "AMMAXWU",
    "AMMAXVU",
    "AMMINWU",
    "AMMINVU",
    "AMSWAPDBB",
    "AMSWAPDBH",
    "AMSWAPDBW",
    "AMSWAPDBV",
    "AMCASDBB",
    "AMCASDBH",
    "AMCASDBW",
    "AMCASDBV",
    "AMADDDBW",
    "AMADDDBV",
    "AMANDDBW",
    "AMANDDBV",
    "AMORDBW",
    "AMORDBV",
    "AMXORDBW",
    "AMXORDBV",
    "AMMAXDBW",
    "AMMAXDBV",
    "AMMINDBW",
    "AMMINDBV",
    "AMMAXDBWU",
    "AMMAXDBVU",
    "AMMINDBWU",
    "AMMINDBVU",
    "EXTWB",
    "EXTWH",
    "CLOW",
    "CLOV",
    "CLZW",
    "CLZV",
    "CTOW",
    "CTOV",
    "CTZW",
    "CTZV",
    "REVBV",
    "REVB2W",
    "REVB4H",
    "REVB2H",
    "REVH2W",
    "REVHV",
    "BITREV4B",
    "BITREV8B",
    "BITREVW",
    "BITREVV",
    "BSTRINSW",
    "BSTRINSV",
    "BSTRPICKW",
    "BSTRPICKV",
    "CRCWBW",
    "CRCWHW",
    "CRCWWW",
    "CRCWVW",
    "CRCCWBW",
    "CRCCWHW",
    "CRCCWWW",
    "CRCCWVW",
    "RDTIMELW",
    "RDTIMEHW",
    "RDTIMED",
    "CPUCFG",
    "FMADDF",
    "FMADDD",
    "FMSUBF",
    "FMSUBD",
    "FNMADDF",
    "FNMADDD",
    "FNMSUBF",
    "FNMSUBD",
    "FMINF",
    "FMIND",
    "FMAXF",
    "FMAXD",
    "FCOPYSGF",
    "FCOPYSGD",
    "FSCALEBF",
    "FSCALEBD",
    "FLOGBF",
    "FLOGBD",
    "FCLASSF",
    "FCLASSD",
    "FFINTFW",
    "FFINTFV",
    "FFINTDW",
    "FFINTDV",
    "FTINTWF",
    "FTINTWD",
    "FTINTVF",
    "FTINTVD",
    "FTINTRPWF",
    "FTINTRPWD",
    "FTINTRPVF",
    "FTINTRPVD",
    "FTINTRMWF",
    "FTINTRMWD",
    "FTINTRMVF",
    "FTINTRMVD",
    "FTINTRZWF",
    "FTINTRZWD",
    "FTINTRZVF",
    "FTINTRZVD",
    "FTINTRNEWF",
    "FTINTRNEWD",
    "FTINTRNEVF",
    "FTINTRNEVD",
    "VMOVQ",
    "XVMOVQ",
    "VPCNTB",
    "VPCNTH",
    "VPCNTW",
    "VPCNTV",
    "XVPCNTB",
    "XVPCNTH",
    "XVPCNTW",
    "XVPCNTV",
    "VSEQB",
    "XVSEQB",
    "VSEQH",
    "XVSEQH",
    "VSEQW",
    "XVSEQW",
    "VSEQV",
    "XVSEQV",
    "LAST",
}
var LOONG64DWARFRegisters = map[int16]int16{}
var Linkloong64 = obj.LinkArch{
    Arch:           sys.ArchLoong64,
    Init:           buildop,
    Preprocess:     preprocess,
    Assemble:       span0,
    Progedit:       progedit,
    DWARFRegisters: LOONG64DWARFRegisters,
}

func DRconv 

func DRconv(a int) string

func IsAtomicInst 

func IsAtomicInst(as obj.As) bool

func OP_12IRR 

func OP_12IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32

func OP_15I 

func OP_15I(op uint32, i uint32) uint32

func OP_16IRR 

func OP_16IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32

func OP_16IR_5I 

func OP_16IR_5I(op uint32, i uint32, r2 uint32) uint32

func OP_B_BL 

func OP_B_BL(op uint32, i uint32) uint32

Encoding for the 'b' or 'bl' instruction.

func OP_IR 

func OP_IR(op uint32, i uint32, r2 uint32) uint32

func OP_IRIR 

func OP_IRIR(op uint32, i1 uint32, r2 uint32, i3 uint32, r4 uint32) uint32

i1 -> msb r2 -> rj i3 -> lsb r4 -> rd

func OP_RR 

func OP_RR(op uint32, r2 uint32, r3 uint32) uint32

r2 -> rj r3 -> rd

func OP_RRR 

func OP_RRR(op uint32, r1 uint32, r2 uint32, r3 uint32) uint32

r1 -> rk r2 -> rj r3 -> rd

func OP_RRRR 

func OP_RRRR(op uint32, r1 uint32, r2 uint32, r3 uint32, r4 uint32) uint32

type Optab 

type Optab struct {
    // contains filtered or unexported fields
}